SYNCHRONOUS COUNTER USING JK FLIPFLOP

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity jkffl is

port(j,k, clk,clr:in std_logic;

q,qbar:out std_logic);

end jkffl;

architecture Behavioral of jkffl is

begin

process(clk,j,k,clr)

variable x:std_logic:='0';

begin

if (clk' event and clk='1') then

case clr  is

when '1'=>

x:='0';

when '0'=> if (j='0' and k='0')then

x:=x;

elsif(j='0' and k='1') then

x:='0';

elsif (j='1' and k='0') then

x:='1';

elsif(j='1' and k='1')then

x:=not x;

end if;

when others=> null;

end case;

end if;

q<= x;

qbar<= not x;

end process;

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity jkcounter is

port(clk,clr:in std_logic;

q,qbar:inout std_logic_vector(3 downto 0));

end jkcounter;

architecture arch of jkcounter is

component jkffl is

port(j,k,clk,clr:in std_logic;

q,qbar:inout std_logic);

end component;

signal k,l,m:std_logic;

begin

k<=q(0);

l<=q(0) and q(1);

m<=q(0) and q(1) and q(2);

a1:jkffl port map('1','1', clk,clr,q(0),qbar(0));

a2:jkffl port map(k,k, clk,clr,q(1),qbar(1));

a3:jkffl port map(l,l, clk,clr,q(2),qbar(2));

a4:jkffl port map(m,m, clk,clr,q(3),qbar(3));

end arch;

CIRCUIT DIAGRAM