VHDL and Verilog Codes

Saturday, 13 July 2013

LEFT SHIFT REGISTER



module fourBit_Reg(clk,d,pad,s,q);
input clk,pad,s;
input [3:0] d;
output q;
reg [3:0] temp;
always @ (posedge clk)
begin
if(s)
temp <= d;
else
temp <= {temp[2:0],pad};
end
assign q = temp[3];
endmodule





OUTPUT WAVEFORM
 
 
Posted by A novice programmer's memo sheet at 07:36
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Blog Archive

  • ▼  2013 (22)
    • ▼  July (22)
      • SYNCHRONOUS BINARY UP-DOWN COUNTER
      • Realization of T FLIP FLOP
      • Realization of T FLIP FLOP
      • Realization of D-FLIP FLOP
      • Realization of SR FLIP FLOP
      • SERIAL IN SERIAL OUT (SISO) REGISTER
      • SYNCHRONOUS COUNTER USING T FLIPFLOP
      • SHIFT REGISTERS USING FPGA
      • COUNTER USING FPGA
      • ALU USING FPGA
      • RIGHT SHIFT REGISTER
      • LEFT SHIFT REGISTER
      • PARALLEL IN PARALLEL OUT (PIPO)
      • PARALLEL IN SERIAL OUT (PISO)
      • SERIAL IN PARALLEL OUT (SIPO) REGISTER
      • ASYNCHRONOUS BINARY UP-DOWN COUNTER
      • ASYNCHRONOUS COUNTER USINGT FLIPFLOP
      • ASYNCHRONOUS COUNTER USING D FLIPFLOP
      • ASYNCHRONOUS COUNTER USING JK FLIPFLOP
      • SYNCHRONOUS COUNTER USING SR FLIPFLOP
      • SYNCHRONOUS COUNTER USING D FLIPFLOP
      • SYNCHRONOUS COUNTER USING JK FLIPFLOP

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