ASYNCHRONOUS COUNTER USINGT FLIPFLOP

library ieee;

use ieee.std_logic_1164.all;

entity tffl is

port (t,clk,clr : in std_logic; q,qbar : inout std_logic);

end tffl;

architecture my_tffarch of tffl is

begin

process (clk,clr,q)

begin

if clr = '1' then

if clk = '1' and clk'event then

q <= t xor q;

qbar <= not (q) after 0.5 ns;

end if;

else

q <= '0';

qbar <= '1';

end if;

end process;

end my_tffarch;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity tcounter is

port(clk,clr:in std_logic;

q,qb:inout std_logic_vector(3 downto 0));

end tcounter;

architecture arch of tcounter is

component tffl is

port(t,clk,clr:in std_logic;

q,qbar:out std_logic);

end component;

signal k,l,m:std_logic;

begin

k<=q (0);

l<=q (1);

m<=q (2);

a1:tffl port map('1',clk,clr,q(0),qb(0));

a2:tffl port map('1',k,clr,q(1),qb(1));

a3:tffl port map('1', l,clr,q(2),qb(2));

a4:tffl port map('1', m,clr,q(3),qb(3));

end arch;

CIRCUIT DIAGRAM