SERIAL IN PARALLEL OUT (SIPO) REGISTER

module my_sipoegister(q,qbar,d,clk,reset);

output [0 :3] q,qbar;

input d,clk,reset;

my_dff sr0 (q[0],qbar[0],d,clk,reset);

my_dff sr1 (q[1],qbar[1],q[0],clk,reset);

my_dff sr2 (q[2],qbar[2],q[1],clk,reset);

my_dff sr3 (q[3],qbar[3],q[2],clk,reset);

endmodule

module my_dff (q,qbar,d,clk,reset);

output q,qbar;

input d,clk,reset;

reg temp0,temp1,temp2,temp3,q,qbar;

always @ (posedge clk or reset )

begin

if (reset)

begin

assign temp0 = !(temp3 && temp1);

assign temp1 = !(temp0 && ~clk);

assign temp2 = !(temp1 && ~clk && temp3);

assign temp3 = ! (temp2 && d);

assign q = !(temp1 && qbar);

assign qbar = !(temp2 && q);

end

else

begin

deassign q;

deassign qbar;

q = 1'b0;

qbar = 1'b1;

end

end

endmodule

CIRCUIT DIAGRAM

 

OUTPUT WAVEFORM