ASYNCHRONOUS BINARY UP-DOWN COUNTER

module my_binupdwncnt (q,qbar,up,clk,reset);

output [0 : 3]q;

output [0 : 3]qbar;

input up,clk,reset,load;

wire [0 : 8] temp;

my_jkffbehaviorvlog ff1 (q[0],qbar[0],load,load,clk,reset);

and (temp[0],up,qbar[0]);

and (temp[1],~up,q[0]);

or (temp[2], temp[1], temp[0]);

my_jkffbehaviorvlog ff2 (q[1],qbar[1], load,load, temp[2], reset);

and (temp[3],up,qbar[1]);

and (temp[4],~up,q[1]);

or (temp[5], temp[3], temp[4]);

my_jkffbehaviorvlog ff3 (q[2],qbar[2], load,load, temp[5],reset);

and (temp[6],up,qbar[2]);

and (temp[7],~up,q[2]);

or (temp[8], temp[3], temp[4]);

my_jkffbehaviorvlog ff4 (q[3],qbar[3], load,load, temp[8],reset);

endmodule

module my_jkffbehaviorvlog (q,qbar,j,k,clk,reset);

output q,qbar;

input j,k,clk,reset;

reg q,qbar;

always @ (negedge clk or  reset)

if (~reset)

begin

q = 1'b0;

qbar = 1'b1;

end

else if (reset)

begin

if (~clk)

begin

if (j==0 && k ==0)

begin

q = q;  qbar = qbar;

end

else if ( j== 0 && k ==1)

begin

q = 1'b0; qbar = 1'b1;

end

else if (j==1 && k == 0)

begin

q = 1'b1; qbar = 1'b0;

end

else if (j ==1 && k ==1)

begin

q = ~q;  qbar = ~qbar;

end

else

begin

q = 1'bz;  qbar = 1'bz;

end

end

end

endmodule;

Result:

Thus the counter is designed in Verilog and the output verified.

CIRCUIT DIAGRAM

OUTPUT WAVEFORM

WHEN UPD=1

WHEN  UPD=0