module my_binupdwncnt (q,qbar,up,clk,reset);
output [0 : 3]q;
output [0 : 3]qbar;
input up,clk,reset;
wire [0 : 3] gorout;
wire [0 : 2] gand1out;
wire [0 : 2] gand2out;
wire down;
not (down,up);
or (gorout[0],up,down);
my_jkffbehaviorvlog ff1
(q[0],qbar[0],gorout[0],gorout[0],clk,reset);
and
(gand1out[0],down,qbar[0]);
and
(gand2out[0],up,q[0]);
or
(gorout[1],gand1out[0],gand2out[0]);
my_jkffbehaviorvlog ff2
(q[1],qbar[1],gorout[1],gorout[1],clk,reset);
and
(gand1out[1],gand1out[0],qbar[1]);
and
(gand2out[1],gand2out[0],q[1]);
or
(gorout[2],gand1out[1],gand2out[1]);
my_jkffbehaviorvlog ff3
(q[2],qbar[2],gorout[2],gorout[2],clk,reset);
and
(gand1out[2],gand1out[1],qbar[2]);
and
(gand2out[2],gand2out[2],q[2]);
or
(gorout[3],gand1out[2],gand2out[2]);
my_jkffbehaviorvlog ff4
(q[3],qbar[3],gorout[3],gorout[3],clk,reset);
endmodule
module
my_jkffbehaviorvlog (q,qbar,j,k,clk,reset);
output q,qbar;
input j,k,clk,reset;
reg q,qbar;
always @ (negedge clk
or reset)
if (~reset)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (reset)
begin
if (~clk)
begin
if (j==0 && k ==0)
begin
q = q;
qbar = qbar;
end
else if ( j== 0 && k ==1)
begin
q = 1'b0; qbar = 1'b1;
end
else if (j==1 && k == 0)
begin
q = 1'b1; qbar = 1'b0;
end
begin
q = ~q; qbar = ~qbar;
end
else
begin
q = 1'bz; qbar = 1'bz;
end
end
end
endmodule
CIRCUIT
DIAGRAM
