ASYNCHRONOUS COUNTER USING D FLIPFLOP

library ieee;

use ieee.std_logic_1164.all;

entity dffl is

port (d,clk,clr : in std_logic; q,qbar : inout std_logic);

end dffl;

architecture my_dffbehaviorarch of dffl is

begin

process (d,clk,clr)

begin

if (clr = '1') then

if (clk = '1') AND (clk'EVENT)  then

q <= d;

qbar <= not (d);

end if;

else

q <= '0';

qbar <= '1';

end if;

end process;

end my_dffbehaviorarch;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity dcounter is

port(clk,clr:in std_logic;

q,qb:inout std_logic_vector(3 downto 0));

end dcounter;

architecture arch of dcounter is

component dffl is

port(d,clk,clr:in std_logic;

q,qbar:out std_logic);

end component;

signal k,l,m:std_logic;

begin

k<=q (0);

l<=q (1);

m<=q (2);

a1:dffl port map('1','1',rst,clk,q(0),qb(0));

a2:dffl port map('1','1',rst,k,q(1),qb(1));

a3:dffl port map('1','1',rst,l,q(2),qb(2));

a4:dffl port map('1','1',rst,m,q(3),qb(3));

end arch;

CIRCUIT DIAGRAM