SYNCHRONOUS COUNTER USING D FLIPFLOP

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity updff is

port (rst,clk:in std_logic;

q,qb:inout std_logic_vector(3 downto 0));

end updff;

architecture Behavioral of updff is

component dff is

port(d,rst,clk: in std_logic;

q,qb: inout std_logic);

end component;

signal a,b,c,d,e,f,g,h,i,j : std_logic;

begin

a<=not q(0);

D1 : dff port map(a,rst,clk,q(0),qb(0));

b<=(q(0) xor q(1));

D2 : dff port map(b,rst,clk,q(1),qb(1));

c<= q(0) and q(1)and qb(2);

d<= qb(0) or qb(1);

e<= q(2) and d ;

j<= c or e;

D3 : dff port map(j,rst,clk,q(2),qb(2));

f<= qb(0) or qb(1) or qb(2);

g<= f and q(3);

h<= q(0) and q(1) and q(2) and qb(3);

i<=g or h;

D4 : dff port map(i,rst,clk,q(3),qb(3));

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff is

port(d,rst,clk: in std_logic;

q,qb: inout std_logic);

end  dff;

architecture Behavioral of dff is

begin

process (clk, rst)

begin

if (rst='0') then

q<='0';

else

if(clk='1' and clk' event) then

if (d='0') then q<='0';

else q<='1';

end if;

end if;

end if;

end process;

qb<=not q;

end Behavioral;

CIRCUIT DIAGRAM