ALU USING FPGA

Aim :

        To design and implement ALU using FPGA.

Tools required :

1.      Xilinx 9.1 ISE software.

2.      FPGA kit

Procedure:

1.      The behavioral simulation of the ALU is obtained using VHDL.

2.      The obtained behavioral description is downloaded to FPGA kit.

3.      The input conditions are checked by assigning constant input at the switches of FPGA kit.

4.      The control switches are changed to verify the various process of  ALU as specified in the program.

ALU DESIGN USING VHDL

library ieee

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity ALU is

port(s : in std_logic_vector(2 down to 0);

         A : in std_logic_vector(2 downto 0);

         B  : in std_logic_vector(2 down to 0);

         F : in std_logic_vector(2 down to 0);

end ALU;

architecture  aluarch of ALU is

begin

     process(s)

begin

    case s is

when “0000”=>

F < ”000”;

when “001”=>

F<=a-b;

when “010”=>

F<b-a;

when “011”=>

F<=a+b;

When “100”=>

F <= a xor b;

When “101”=>

F<=a or b;

when  “110”=>

F<=a and b;

when  others=>

F<”111”;

end case;

end process;

end behavioural;

ALU DESIGN USING VERILOG

module alu(a,b, sel, out);

input [7:0] a,b;

input [3:0] sel;

output [7:0] out;

reg [7:0]out;

always @(a or b or sel)

case (sel)

4'b0000:out<=a+b;

4'b0001:out<=a-b;

4'b0010:out<=a+1;

4'b0011:out<=b+1;

4'b0100:out<=a-1;

4'b0101:out<=b-1;

4'b0110:out<=8'd0;

4'b0111:out<=8'hff;

4'b1000:out<=a&b;

4'b1001:out<=a|b;

4'b1010:out<=a^b;

4'b1011:out<=~a;

4'b1100:out<=~b;

endcase

endmodule

Result :

      The ALU is designed and implemented using FPGA kit.

UCF

NET "a<0>"  LOC = "p204"  ;

NET "a<1>"  LOC = "p194"  ;

NET "a<2>"  LOC = "p184"  ;

NET "a<3>"  LOC = "p183"  ;

NET "a<4>"  LOC = "p175"  ;

NET "a<5>"  LOC = "p174"  ;

NET "a<6>"  LOC = "p169"  ;

NET "a<7>"  LOC = "p159"  ;

NET "b<0>"  LOC = "p154"  ;

NET "b<1>"  LOC = "p148"  ;

NET "b<2>"  LOC = "p142"  ;

NET "b<3>"  LOC = "p136"  ;

NET "b<4>"  LOC = "p130"  ;

NET "b<5>"  LOC = "p124"  ;

NET "b<6>"  LOC = "p118"  ;

NET "b<7>"  LOC = "p110"  ;

NET "z<0>"  LOC = "p200"  ;

NET "z<1>"  LOC = "p199"  ;

NET "z<2>"  LOC = "p197"  ;

NET "z<3>"  LOC = "p196"  ;

NET "z<4>"  LOC = "p193"  ;

NET "z<5>"  LOC = "p192"  ;

NET "z<6>"  LOC = "p190"  ;

NET "z<7>"  LOC = "p189"  ;

NET "sel<0>"  LOC = "p116"  ;

NET "sel<1>"  LOC = "p115"  ;

NET "sel<2>"  LOC = "p113"  ;

NET "sel<3>"  LOC = "p112"  ;