SYNCHRONOUS COUNTER USING T FLIPFLOP

VHDL
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
entity tcounter is

port(clk,rst:in std_logic; 
q,qbar:inout std_logic_vector(3 downto 0));

end tcounter;

architecture Behavioral of tcounter is 
component tffl is

port(t,rst,clk:in std_logic;

q,qb:out std_logic);

end component;
signal k,l,m:std_logic; 
begin
k<=q(0);

l<=q(0) and q(1);

m<=q(0) and q(1) and q(2); 
a1:tffl port map('1',rst,clk,q(0),qbar(0)); 
a2:tffl port map(k,rst,clk,q(1),qbar(1)); 
a3:tffl port map(l,rst,clk,q(2),qbar(2));
a4:tffl port map(m,rst,clk,q(3),qbar(3)); 
end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; 
entity tffl is 
port(t,rst,clk:in std_logic;

q,qb:out std_logic); 
end tffl;

architecture Behavioral of tffl is
begin
process
variable x:std_logic:='0'; 
begin
wait on clk ; 
if (clk' event and clk='1') then

if rst='1' then

x:='0';
elsif t='1' then

x:=not x;
else x:=x;

end if;

end if;

q<=x;

qb<=not x;
end process;

end Behavioral;

VERILOG

module my_syncbincnt (q,qbar,load,clk,reset);

output [0 : 3] q;

output [0 : 3] qbar;

input load,clk,reset;

wire [0 : 1] temp;

my_tffbehaviorvlog ff1 (q[0],qbar[0],load, clk,reset);

my_tffbehaviorvlog ff2 (q[1],qbar[1],q[0], clk,reset);

and (temp[0],q[0],q[1]);

my_tffbehaviorvlog ff3 (q[2],qbar[2],temp[0], clk,reset);

and (temp[1],q[2],q[0],q[1]);

my_tffbehaviorvlog ff4 (q[3],qbar[3],temp[1], clk,reset);

endmodule

module my_tffbehaviorvlog (q,qbar,t,clk,reset);

output q,qbar;

input t,clk,reset;

reg q,qbar;

always @ (reset or posedge clk)

if (reset)

begin

q = 1'b0;

qbar = 1'b1;

end

else

begin

q = t^q;

qbar = ~q;

end

endmodule

CIRCUIT DIAGRAM