PARALLEL IN SERIAL OUT (PISO)

module innerblock (out,s,l,i,q);

output out;

input s,l,i,q;

wire andod,andevn;

and od (andod,q,s);

and ev (andevn,i,l);

xor xr (out,andod,andevn);

endmodule

module my_piso (q,qbar,i,clk,reset,shift);

output [0 : 3] q;

output [0 : 3] qbar;      

input [0 : 3] i;

input clk,reset,shift;

wire [0 : 2]gxr;

wire load;

not n1 (load,shift);

my_dff d0 (q[0],qbar[0],i[0],clk,reset);

innerblock i1 (gxr[0],shift,load,i[1],q[0]);

my_dff d1(q[1],qbar[1],gxr[0],clk,reset);

innerblock i2 (gxr[1],shift,load,i[2],q[1]);

my_dff d2(q[2],qbar[2],gxr[1],clk,reset);

innerblock i3 (gxr[2],shift,load,i[3],q[2]);

my_dff d3(q[3],qbar[3],gxr[2],clk,reset);

endmodule

module my_dff (q,qbar,d,clk,reset);

output q,qbar;

input d,clk,reset;

reg temp0,temp1,temp2,temp3,q,qbar;

always @ (posedge clk or reset )

begin

if (reset)

begin

assign temp0 = !(temp3 && temp1);

assign temp1 = !(temp0 && ~clk);

assign temp2 = !(temp1 && ~clk && temp3);

assign temp3 = ! (temp2 && d);

assign q = !(temp1 && qbar);

assign qbar = !(temp2 && q);

end

else

begin

deassign q;

deassign qbar;

q = 1'b0;

qbar = 1'b1;

end

end

endmodule

CIRCUIT DIAGRAM

 

OUTPUT WAVEFORM