library ieee;
entity my_srffbehavior is
port (s,r,clk,clr : in std_logic; q,qbar : inout std_logic);
end my_srffbehavior;
architecture my_srffbehaviorarch of my_srffbehavior is
begin
process (clk,clr)
begin
if (clr = '0') then
q <= '0'; qbar <= '1';
else
if (clk = '1') AND (clk'EVENT) then
if (s = '0') then
if (r = '0') then
q <= q ; qbar <= qbar ;
else
q <= '0' ; qbar <= '1' ;
end if;
else
if (r = '0') then
q <= '1' ; qbar <= '0';
else
q <= 'U' ; qbar <= 'U' ;
end if;
end if;
end process;
end my_srffbehaviorarch;
TRUTH TABLE:
INPUT
|
OUTPUT
| |
S
|
R
|
Qn+1
|
0
0
1
1
|
0
1
0
1
|
Qn
0
1
X
|
LOGIC DIAGRAM:
OUTPUT WAVEFORM
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