library ieee;
use ieee.std_logic_1164.all;
entity my_tff is
port (t,clk,clr : in std_logic; q,qbar : inout std_logic);
end my_tff;
architecture my_tffarch of my_tff is
begin
process (clk,clr,q)
begin
if clr = '1' then
if clk = '1' and clk'event then
q <= t xor q;
qbar <= not (q) after 0.5 ns;
end if;
else
q <= '0';
qbar <= '1';
end if;
end process;
end my_tffarch;
TRUTH TABLE:
INPUT
|
OUTPUT
|
T
|
Qn+1
|
0
1
|
Qn
Qn’
|
LOGIC DIAGRAM:
OUTPUT WAVEFORM
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