SHIFT REGISTERS USING FPGA

Aim :

        To design and implement shift register using FPGA.

Tools required :

1.      Xilinx 9.1 ISE software.

2.      FPGA kit

Procedure:

1.      The behavioral simulation of the shift register is obtained using VHDL.

2.      The obtained behavioral description is downloaded to FPGA kit.

3.      The input conditions are checked by assigning constant input at the switches of FPGA kit.

4.      The control switches are changed to verify the various process of shift register as specified in the program.

VHDL

SISO

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sin_sout is

Port ( clk  : in  STD_LOGIC;

sin  : in  STD_LOGIC;

sout : out STD_LOGIC);

end sin_sout;

architecture Behavioral of sin_sout is

signal tmp: std_logic_vector(3 downto 0);

begin

process (clk)

begin

if (clk' event and clk='1') then

tmp <= tmp(2 downto 0)& sin;

end if;

end process;

sout <= tmp(3);

end Behavioral;

UCF

NET "clk"  LOC = "P178"  ;

NET "pout"  LOC = "P200"  ;

NET "sin"  LOC = "P106"  ;

SIPO

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sin_pout is

Port ( clk  : in  STD_LOGIC;

sin  : in  STD_LOGIC;

pout : out STD_LOGIC_VECTOR (7 downto 0));

end sin_pout;

architecture Behavioral of sin_pout is

signal tmp: std_logic_vector(7 downto 0);

begin

process (clk)

begin

if (clk' event and clk='1') then

tmp <= tmp(6 downto 0)& sin;

end if;

end process;

pout <= tmp;

end Behavioral;

UCF

NET "clk"  LOC = "P178"  ;

NET "pout<0>"  LOC = "P200"  ;

NET "pout<1>"  LOC = "P199"  ;

NET "pout<2>"  LOC = "P197"  ;

NET "pout<3>"  LOC = "P196"  ;

NET "pout<4>"  LOC = "P193"  ;

NET "pout<5>"  LOC = "P192"  ;

NET "pout<6>"  LOC = "P190"  ;

NET "pout<7>"  LOC = "P189"  ;

NET "sin"  LOC = "P106"  ;

PIPO

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sin_pout is

Port ( clk  : in  STD_LOGIC;

pin  : in  STD_LOGIC_VECTOR (3 downto 0);

pout : out STD_LOGIC_VECTOR (3 downto 0));

end sin_pout;

architecture Behavioral of sin_pout is

signal tmp: std_logic_vector(3 downto 0);

begin

process (clk)

begin

if (clk' event and clk='1') then

tmp <= pin;

end if;

end process;

pout <= tmp;

end Behavioral;

UCF

NET "clk"  LOC = "P178"  ;

NET "pout<0>"  LOC = "P200"  ;

NET "pout<1>"  LOC = "P199"  ;

NET "pout<2>"  LOC = "P197"  ;

NET "pout<3>"  LOC = "P196"  ;

NET "pin<0>"  LOC = "P106"  ;

NET "pin<1>"  LOC = "P107"  ;

NET "pin<2>"  LOC = "P108"  ;

NET "pin<3>"  LOC = "P109"  ;

PISO

Library IEEE;
 Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Entity piso is
Port( D : in std_logic_vector(2 downto 0);
         CLK : in std_logic;
         Q : inout std_logic_vector(2 downto 0);
         QBAR : inout std_logic_vector(2 downto 0));
 End piso;
Architecture behaviour of piso is
signal shift_reg : std_logic_vector(7 downto 0);
if load = '1'
then shift_reg <= data_in;
else
shift_reg <= '0'&shift_reg(7 downto 1);
 end if;
data_out <= shift_reg(0);
End behaviour;

UCF

NET "clk"  LOC = "P178"  ;

NET "pout<0>"  LOC = "P200"  ;

NET "pin<0>"  LOC = "P106"  ;

NET "pin<1>"  LOC = "P107"  ;

NET "pin<2>"  LOC = "P108"  ;

NET "pin<3>"  LOC = "P109"  ;

VERILOG

SISO

module shiftReg ( in, clk, reset,out);
input clk,reset;
input in;
output out;
reg  out;
wire q0,q1,q2;
always @ (posedge clk)
begin
 if (reset)
q0= 4'b0;
q1= 4'b0;
q2= 4'b0;
else
assign q0=in;
assign q1=q0;
assign q2=q1;
assign out= q2;
end

UCF

NET "clk"  LOC = "P178"  ;

NET "pout"  LOC = "P200"  ;

NET "sin"  LOC = "P106"  ;

SIPO

module shiftReg ( in, clk, reset,q);
input in,clk,reset;
output [0:3]q;
reg  [0:3] q;
always @ (posedge clk)
begin
 if (reset)
q<= 4'b0;
else
assign q[0]=in;
assign q[1]=q[0];
assign q[2]=q[1];
assign q[3]= q[2];
end

UCF

NET "clk"  LOC = "P178"  ;

NET "pout<0>"  LOC = "P200"  ;

NET "pout<1>"  LOC = "P199"  ;

NET "pout<2>"  LOC = "P197"  ;

NET "pout<3>"  LOC = "P196"  ;

NET "pout<4>"  LOC = "P193"  ;

NET "pout<5>"  LOC = "P192"  ;

NET "pout<6>"  LOC = "P190"  ;

NET "pout<7>"  LOC = "P189"  ;

NET "sin"  LOC = "P106"  ;

PIPO

module shiftReg ( in, clk, reset,q);
input clk,reset;
input [0:3]in;
output [0:3]q;
reg  [0:3] q;
always @ (posedge clk)
begin
 if (reset)
q<= 4'b0;
else
assign q[0]=in[0];
assign q[1]=in[1];
assign q[2]=in[2];
assign q[3]= in[3];
end

UCF

NET "clk"  LOC = "P178"  ;

NET "pout<0>"  LOC = "P200"  ;

NET "pout<1>"  LOC = "P199"  ;

NET "pout<2>"  LOC = "P197"  ;

NET "pout<3>"  LOC = "P196"  ;

NET "pin<0>"  LOC = "P106"  ;

NET "pin<1>"  LOC = "P107"  ;

NET "pin<2>"  LOC = "P108"  ;

NET "pin<3>"  LOC = "P109"  ;

PISO

module shiftReg ( out, in, clk, reset);
input clk,reset;
input [3:0]in;
output out;
reg  out;
always @ (posedge clk)
begin
 if (reset)
mem <= 4'b0;
else
 mem <= {in,mem};
 end

UCF

NET "clk"  LOC = "P178"  ;

NET "pout<0>"  LOC = "P200"  ;

NET "pin<0>"  LOC = "P106"  ;

NET "pin<1>"  LOC = "P107"  ;

NET "pin<2>"  LOC = "P108"  ;

NET "pin<3>"  LOC = "P109"  ;