library ieee;
use ieee.std_logic_1164.all;
entity my_dffbehavior is
port (d,clk,clr : in std_logic; q,qbar : inout std_logic);
end my_dffbehavior;
architecture my_dffbehaviorarch of my_dffbehavior is
begin
process (d,clk,clr)
begin
if (clr = '1') then
if (clk = '1') AND (clk'EVENT) then
q <= d; qbar <= not (d);
end if;
else
q <= '0'; qbar <= '1';
end if;
end process;
TRUTH TABLE:
INPUT
|
OUTPUT
|
D
|
QN+1
|
0
|
0
|
1
|
1
|
LOGIC DIAGRAM:
OUTPUT WAVEFORM
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