VHDL and Verilog Codes
Saturday, 13 July 2013
LEFT SHIFT REGISTER
module fourBit_Reg(clk,d,pad,s,q);
input clk,pad,s;
input [3:0] d;
output q;
reg [3:0] temp;
always @ (posedge clk)
begin
if(s)
temp <= d;
else
temp <= {temp[2:0],pad};
end
assign q = temp[3];
endmodule
OUTPUT WAVEFORM
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