Aim :
To
design and implement counter using FPGA.
Tools required :
1. Xilinx
9.1 ISE software.
2. FPGA kit
Procedure:
1. The
behavioral simulation of the counter is
obtained .
2. The
obtained behavioral description is downloaded to FPGA kit.
3. The
input conditions are checked by assigning constant input at the switches of
FPGA kit.
4. The
control switches are changed to verify the various process of counter as
specified in the program.
VHDL
BINARY
UP COUNTER
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
counter_4 is
Port (
rst : in STD_LOGIC;
clk :
in STD_LOGIC;
en : in
STD_LOGIC;
q : out
STD_LOGIC_VECTOR (3 downto 0));
end counter_4;
architecture
Behavioral of counter_4 is
signal
Pre_q: std_logic_vector(3 downto 0);
begin
process
(clk, rst, en)
begin
if (rst
= '1') then
pre_q
<= "0000";
elsif
(clk' event and clk = '1') then
if (en =
'1') then
pre_q
<= pre_q + 1;
end if;
end if;
end
process;
q <=
pre_q;
end
Behavioral;
BINARY
DOWN COUNTER
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
downcounter_4 is
Port (
rst : in STD_LOGIC;
clk :
in STD_LOGIC;
en : in STD_LOGIC;
q : out
STD_LOGIC_VECTOR (3 downto 0));
end
counter_4;
architecture
Behavioral of counter_4 is
signal
Pre_q: std_logic_vector(3 downto 0);
begin
process
(clk, rst, en)
begin
if (rst
= '1') then
pre_q
<= "0000";
elsif
(clk' event and clk = '1') then
if (en =
'1') then
pre_q
<= pre_q - 1;
end if;
end if;
end
process;
q <=
pre_q;
end
Behavioral;
BINARY
UP/DOWN COUNTER
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
udcounter_4 is
Port (
rst : in STD_LOGIC;
clk :
in STD_LOGIC;
ud : in
STD_LOGIC;
q : out
STD_LOGIC_VECTOR (3 downto 0));
end
udcounter_4;
architecture
Behavioral of udcounter_4 is
signal
Pre_q: std_logic_vector(3 downto 0);
begin
process
(clk, rst, ud)
begin
if (rst
= '1') then
pre_q
<= "0000";
elsif
(clk' event and clk = '1') then
if (ud =
'1') then
pre_q
<= pre_q + 1;
else
pre_q
<= pre_q - 1;
end if;
end if;
end
process;
q <=
pre_q;
end
Behavioral;
VERILOG
BINARY UP COUNTER
module
first_counter (clk, reset, enable , out );
input
clock ;
input
reset ;
input
enable ;
output
[3:0] out ;
wire
clock ;
wire
reset ;
wire
enable ;
reg [4:0]
out ;
always @
(posedge clock)
if (reset == 1'b1) begin
out
<= 4'b0000;
end
else if (enable == 1'b1) begin
out
<= out + 1;
end
end
endmodule
BINARY DOWN COUNTER
input clock ;
input reset ;
input enable ;
output [3:0] out ;
wire clock ;
wire reset ;
wire enable ;
reg [4:0] out ;
always @ (posedge clock)
if (reset == 1'b1) begin
out <= 4'b1111;
end
else if (enable == 1'b1) begin
out <= out - 1;
end
end
endmodule
BINARY UP/DOWN COUNTER
module updown_behavld(q,clk,ctrl,data,rst,ld);
input clk,ctrl,rst,ld;
input [3:0]data;
output [3:0]q;
reg [3:0] count;
always @(posedge clk)
begin
if(rst)
count <= 4'b0000;
else if(ld)
count <= data;
else if(ctrl)
count<=count+1;
else
count <= count-1;
end
assign q=count;
endmodule
Result :
The design and implementation of counter
unit is verified.
UCF
NET "clk" LOC = "P178" ;
NET "en" LOC = "P106" ;
NET
"q<0>" LOC =
"P200" ;
NET
"q<1>" LOC =
"P199" ;
NET
"q<2>" LOC =
"P197" ;
NET
"q<3>" LOC =
"P196" ;
NET "rst" LOC = "P126" ;
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